Gurunadha Mangalampeta is a highly accomplished Senior Verification Infrastructure Engineer with over 25 years of experience in ASIC and SoC verification across simulation and system-level environments. He has extensive expertise in developing scalable UVM-based verification frameworks, integrating industry-standard VIPs, and enabling efficient IP, subsystem, and full-chip validation for high-performance compute architectures. Throughout his career, he has contributed to several leading semiconductor and technology organizations, including MatX AI, Ampere Computing, SK hynix, Marvell Technology, Oracle Corporation, Intel, and Broadcom. His work has focused on advanced memory subsystems, cache coherency, ARM CHI interconnects, PCIe, CXL, HBM3, and next-generation server-class SoCs. Gurunadha specializes in SystemVerilog, UVM, performance verification, cache coherency protocols, and scalable verification methodologies. He has successfully led verification strategy development, architected reusable verification infrastructures, and driven complex silicon programs from architecture definition through tapeout. His technical strengths include debugging complex coherency and memory subsystem issues, automation, constrained-random verification, and full-system simulation environments. He holds advanced qualifications in VLSI Design and Digital Systems from Indian Institute of Science and Jawaharlal Nehru Technological University. He is also a Senior Member of IEEE and a Fellow Member of Institution of Electronics and Telecommunication Engineers. In addition to his industry contributions, Gurunadha is actively involved in publishing and reviewing technical research and has a strong interest in emerging technologies related to AI-driven semiconductor verification and intelligent computing systems.        

Intelligent Verification Frameworks for Next-Generation SoCs: AI-Driven Approaches for Scalable Coverage Closure   As modern System-on-Chip (SoC) architectures continue to scale in complexity, functional verification has become the dominant bottleneck in the semiconductor development lifecycle. The adoption of next-generation interconnect protocols such as PCIe 6.0 and Compute Express Link (CXL), together with high-bandwidth memory technologies like HBM4, has significantly increased verification complexity, exposing the scalability limitations of traditional constrained-random and UVM-based methodologies.   This paper examines the evolution of SoC verification from manual, coverage-driven approaches toward intelligent, machine learning-assisted verification frameworks. It explores how generative AI techniques, adaptive stimulus generation, and predictive coverage analytics can improve verification efficiency and accelerate coverage closure. The paper also highlights the growing synergy between hybrid simulation–formal verification methodologies and data-driven learning models in addressing increasingly complex protocol interactions and corner-case validation challenges. Finally, it presents a forward-looking perspective on autonomous verification environments designed to support the next generation of AI-centric and high-performance computing systems.