FutureTech 2026: Artificial Intelligence, Quantum Computing & Intelligent Computing Systems

Theme: Transforming the Future: AI and Quantum Computing for a Smarter World

08-09, September 2026 Virtual, Virtual, Virtual
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Smith Neba Chi
Featured Speaker

Smith Neba Chi

Session Speaker

Cameroon

Biography

Smith Neba Chi is a versatile Cameroonian cybersecurity analyst, academic researcher, and technology consultant known for his cross-disciplinary career. He bridges the gap between deep mathematical security theory and live digital protection infrastructure. He serves as a Predoctoral Research Fellow and Graduate Intern at the University of Bamenda's Centre for Cybersecurity and Mathematical Cryptology, working on the FPGA optimization of the Unbalanced Oil and Vinegar (UOV) multivariate quadratic equations-based Post-Quantum Cryptography (PQC) scheme to defend data against future quantum-computing threats. He explores not just the academic aspects of Cybersecrity, but the professional, being a Certified Ethical Hacker (CEH), he acts as a Cybersecurity Analyst and consultant. In this space, he makes sure that the top security measures are implemented during the development and deployment of IT solutions and infrastructure auditing to safeguard corporate digital assets.

Abstract Title

High-Throughput and Resource-Efficient Hardware Architecture for Galois Field Multiplier Galois field $GF(2^m)$ arithmetic is a foundational operation across a broad range of cryptographic protocols, underlying symmetric ciphers, error-correcting and authentication codes, and a growing class of public-key schemes. As these protocols are increasingly deployed on resource- and power-constrained platforms while still being required to meet strict real-time latency budgets, the efficiency of the underlying field multiplier directly determines whether a given protocol can be protected in practice. Software implementations of $GF(2^m)$ multiplication struggle to meet combined resource and timing constraints of this kind, particularly at the larger field sizes required by elliptic-curve cryptography, which is what motivates dedicated hardware acceleration. Yet hardware multipliers for this operation are typically designed and validated for a single fixed field size, so a design characterized at $GF(2^8)$ offers no direct evidence about its behaviour at $GF(2^{163})$ or larger, and conversely a design intended to scale to cryptographic field sizes is rarely first validated against a small, well-understood case.We address this by presenting a single, parametrized $GF(2^m)$ multiplier architecture, instantiated and measured at $GF(2^8)$ before being generalized across field sizes relevant to byte-oriented cryptographic primitives and to the NIST/SEC2 binary elliptic curves ($GF(2^{163})$ through $GF(2^{571})$). At $GF(2^8)$, the architecture synthesizes to a purely combinational, single-cycle multiplier occupying 33 look-up tables and zero flip-flops on a Xilinx Artix-7 device, two fewer LUTs than a recent cyclic-code fault-detecting multiplier targeting the same field, and without that design's fault-detection overhead. Because a direct partial-product array grows quadratically in $m$, we generalize the same construction with a recursive Karatsuba–Ofman decomposition, extended to arbitrary field degree via uneven splits rather than restricted to powers of two, so that the odd degrees used by the standard binary curves are supported directly. We give an operation-count analysis identifying the field size beyond which the recursive decomposition is expected to outperform the direct array, and we report synthesis results across the full range of target sizes on the device used to validate the base case.